1. Field of the Invention
The present invention relates in general to the field of data processing circuitry and, more specifically, to systems and methods for improving data processing circuit performance by reducing the effects of hysteresis in Silicon on Insulator (SOI) technology.
2. Description of the Related Art
Source Synchronous Bus (SSB) timing is a technique typically used to distribute high speed data from one point of the chip to another. In source synchronous (SS) channels, one or multiple data streams are bundled together with a clock signal that are all generated in a transmitter circuit and travel through long distances on-chip to a receiver circuit that uses the same clock to capture the sent data. SS methodology is an extremely robust distribution technique, as it allows cancellation of all forms of systematic variations that affect both the data and clock lines.
In SOI, over the usual sources of process variation like die-to-die or random/systematic mismatch On-Chip Variation (OCV), there is an additional source of variation called hysteresis. Hysteresis is due to a memory effect where the previous switching activity influences the threshold voltage of the SOI transistor in a subsequent switching activity. The threshold voltage typically stabilizes after a large number of switching events.
Therefore, in the design of SS channels in an SOI process, a significant amount of additional guard-band is added to cover for hysteresis-related effects that lead to increased latency of point-to-point communication, and increased active and leakage power consumption. Likewise, in the design of a CMOS implementation in an SOI process, a significant amount of additional guard-band is added to cover for hysteresis-related effects that can lead to increased latency for wake-up period during chip initialization, point-to-point communication, increased active and leakage-power consumption.
In view of the foregoing, it is apparent that there is a need for improved systems and methods for reducing the effects of hysteresis in data processing circuits.
Where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.